搜索资源列表
1024_FFT
- 1024点FFT快速傅立叶变换，包含说明文档和VHDL源代码，16位输入/输出，带DMA功能，xilinx的ip-1024-point FFT fast Fourier transform, and includes documentation, VHDL source code, 16 input / output, with DMA function, the ip xilinx
FFT_IP
- Xilinx FPGA 的IP核，实现FFT功能的-Xilinx FPGA IP core, FFT function
81i_radix2_xfft1024_v3_2
- xilinx FFT using ip core project navigator-xilinx ip using FFT core project navigator
fftipcore
- 该程序是vhdl语言编写的fft变换的ip核代码，程序中共包含了36个.vhd文件-that the procedure was prepared by the vhdl language fft transform ip nuclear code CPC procedures contained 36. vhd documents
fft_IPcore
- 这是一个fft的IP核，安装要求为quartus6.0以上。解压安装后可在quartus里例化使用，元件主要为cyclone和stratix,最大支持1024点的转换。
STFT
- 短时傅里叶变换的FPGA实现零重复度使用了fft的IP核设计-When the Fourier transform of the FPGA to achieve zero repeatability using fft IP core design
fftip_1k
- FFT IP核调用 VHDL语言 quartus -FFT IP core VHDL language called quartus
FFTPVerilog
- FFT Verilog RTL 经过测试与Altera FFT IP相当-FFT Verilog RTL Altera FFT IP
fft_test
- ALTERA的FFT IP核时序的仿真，verilog语言。采用burst方式，FFT点数2048点-FFT IP core of timing simulation ALTERA, verilog language. Using burst mode, FFT points 2048 points
fft-IPcore
- verilog编写，基于ISEfft的ip核研究，数据生成采用matlab，有仿真截图-verilog written, ip nuclear research ISEfft based on data generated using matlab, there are simulation screenshot
fft512_ipcore
- 512点的FFT 使用IP核 帮助新手理解-Using a 512-point FFT IP core to help the novice to understand
FFT
- 基于Altera Cyclone II 系列FPGA嵌入高性能的嵌入式IP核(Nios)处理器软核,实现了基于FFT的音频信号分析-Altera Cyclone II FPGA family based embedded high-performance embedded IP core (Nios) soft core processor to achieve a FFT-based audio signal analysis
fft_512
- 采用Xilinx提供的VHDL FFT ip核实现512点FFT，可以实现使能控制、时钟控制等功能-Using Xilinx provides VHDL FFT ip core to achieve implementation of 512 points FFT, with enable control, clock control and other functions
fft
- 基于fpga的fft变换，用ip核实现。用vhdl编写-Fpga based fft transform, use ip core implementation. Written in vhdl
cf-fft
- 用ip核实现fft。用vhdl编写。altera的fpga-Ip core implementation using fft. Written in vhdl
fft_streaming
- 关于QuartusII FFT ip核的使用，采用Streaming模式，包含Modelsim仿真程序-About QuartusII FFT ip nuclear use, using Streaming mode, including Modelsim simulation program
FFT
- verilog xilinx IP实现FFT仿真-Verilog xilinx IP implementation FFT simulation
fft512
- 基于verilog IP核的FFT工程，512位FFT运算，(FFT engineering based on Verilog IP kernel and 512 bit FFT operation,)
pipelined_fft_64-master
- Pipelined FFT/IFFT 64 points (Fast Fourier Transform) IP Core User Manual
exp_fft_test_724
- 在quartus软件中调用FFT的IP核，编辑IP核的驱动模块，使得IP核读入数据进行处理，输出数据。使用modelsim进行联合仿真。(In the quartus software, the IP kernel of FFT is called, and the driver module of the IP kernel is edited, so that the IP kernel is read into the data for processing and output data